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| LEADER |
01400cam a2200373 4500 |
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PPN174470932 |
| 003 |
http://www.sudoc.fr/174470932 |
| 005 |
20230710130700.0 |
| 010 |
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|a 978-0-387-25538-5
|b alk. paper
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| 010 |
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|a 0-387-25538-9
|b alk. paper
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| 035 |
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|a (OCoLC)757383940
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| 100 |
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|a 20131126d2006 k y0frey0103 ba
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| 101 |
0 |
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|a eng
|2 639-2
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| 102 |
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|a US
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| 105 |
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|a a a 001|y
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| 106 |
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|a r
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| 181 |
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|6 z01
|c txt
|2 rdacontent
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| 181 |
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1 |
|6 z01
|a i#
|b xxxe##
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| 182 |
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|6 z01
|c n
|2 rdamedia
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1 |
|6 z01
|a n
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| 200 |
0 |
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|a Verification methodology manual for SystemVerilog
|f by Janick Bergeron ... [et al.]
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| 210 |
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|a New York
|c Springer
|d cop. 2006
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| 215 |
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|a 1 vol. (xvii-503 p.)
|c ill.
|d 24 cm
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| 320 |
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|a Bibliogr.. Index
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| 452 |
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|0 113270348
|t Verification methodology manual for systemverilog
|f Janick Bergeron, Eduard Cerny, Alan Hunter ... [et al.]
|d 2006
|c New York, NY
|n Springer US
|n Imprint: Springer
|y 0-387-25556-7
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| 606 |
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|3 PPN050283170
|a Verilog (langage de description de matériel informatique)
|2 rameau
|
| 606 |
|
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|3 PPN027223221
|a Circuits intégrés
|3 PPN027794725
|x Conception et construction
|2 rameau
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| 676 |
|
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|a 621.39/2
|v 22
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| 680 |
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|a TK7885.7
|b .V44 2006
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| 700 |
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1 |
|3 PPN17447153X
|a Bergeron
|b Janick
|4 070
|
| 801 |
|
3 |
|a FR
|b Abes
|c 20210427
|g AFNOR
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| 801 |
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0 |
|b DLC
|g AACR2
|
| 930 |
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|5 441092104:49432306X
|b 441092104
|j u
|
| 998 |
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|a 663423
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