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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : 22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected Papers
This book constitutes the refereed proceedings of the 22nd International Conference on Integrated Circuit and System Design, PATMOS 2012, held in Newcastle, UK Spain, in September 2012. The 25 revised full papers presented were carefully reviewed and selected from numerous submissions. The paper fea...
| Auteurs principaux : | , , |
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| Format : | Livre |
| Langue : | anglais |
| Titre complet : | Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : 22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected Papers / edited by José L. Ayala, Delong Shang, Alex Yakovlev. |
| Publié : |
Berlin, Heidelberg :
Springer Berlin Heidelberg
, [20..] Cham : Springer Nature |
| Collection : | Theoretical computer science and general issues (Online) |
| Accès en ligne : |
Accès Nantes Université
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| Condition d'utilisation et de reproduction : | Conditions particulières de réutilisation pour les bénéficiaires des licences nationales : https://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 |
| Sujets : | |
| Documents associés : | Autre format:
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Autre format: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation |
- Sleep-Transistor Based Power-Gating Tradeoff Analyses
- Modelling and Analysis of Manufacturing Variability Effects from Process to Architectural Level
- Non-invasive Power Simulation at System-Level with SystemC
- A Standard Cell Optimization Method for Near-Threshold Voltage Operations
- An Extended Metastability Simulation Method for Synchronizer Characterization
- Phase Space Based NBTI Model
- Fast Propagation of Hamming and Signal Distances for Register-Transfer Level Datapaths
- Noise Margin Based Library Optimization Considering Variability in Sub-threshold
- TCP Window Based DVFS for Low Power Network Controller SoC
- A Generic Architecture for Robust Asynchronous Communication Links
- Direct Statistical Simulation of Timing Properties in Sequential Circuits
- On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture
- Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications
- Design of a 150 mV Supply, 2 MIPS, 90nm CMOS, Ultra-Low-Power Microprocessor
- Run-Time Measurement of Harvested Energy for Autarkic Sensor Operation
- Observability Conditions and Automatic Operand-Isolation in High-Throughput Asynchronous Pipelines
- Dynamic Power Management of a Computer with Self Power-Managed Components
- Case Studies of Logical Computation on Stochastic Bit Streams.