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| LEADER |
01111cam a2200337 4500 |
| 001 |
PPN127971602 |
| 005 |
20141218095900.0 |
| 010 |
|
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|a 978-1-420-06094-2
|b rel.
|
| 010 |
|
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|a 1-420-06094-5
|
| 020 |
|
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|a US
|b 2007044293
|
| 020 |
|
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|a GB
|b A781905
|
| 100 |
|
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|a 20081006d2008 k y0frey0103 ba
|
| 101 |
0 |
|
|a eng
|
| 102 |
|
|
|a US
|
| 105 |
|
|
|a a a 001yy
|
| 106 |
|
|
|a r
|
| 200 |
1 |
|
|a Introduction to logic design
|b Texte imprimé
|f Svetlana N. Yanushkevich, Vlad P. Shmerko
|
| 210 |
|
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|a Boca Raton
|c CRC Press
|d cop. 2008
|
| 215 |
|
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|a 1 vol.(XXII-692 p.)
|c ill.
|d 24 cm
|
| 320 |
|
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|a Bibliogr. Index
|
| 606 |
|
|
|3 PPN027449416
|a Circuits logiques
|2 rameau
|
| 606 |
|
|
|3 PPN027723275
|a Conception assistée par ordinateur
|2 rameau
|
| 606 |
|
|
|3 PPN027895823
|a Circuits intégrés à très grande échelle
|2 rameau
|
| 700 |
|
1 |
|3 PPN12821340X
|a Yanushkevich
|b Svetlana N.
|4 070
|
| 702 |
|
1 |
|3 PPN128213442
|a Shmerko
|b Vlad P.
|4 070
|
| 801 |
|
3 |
|a FR
|b Abes
|c 20081014
|g AFNOR
|
| 801 |
|
0 |
|b DLC
|g AACR2
|
| 801 |
|
2 |
|b UKM
|g AACR2
|
| 930 |
|
|
|5 441842101:348799195
|b 441842101
|a 621.395 YAN
|j u
|
| 979 |
|
|
|a STN
|
| 998 |
|
|
|a 541679
|
Nantilus
