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| LEADER |
01816nam a2200397 4500 |
| 001 |
PPN121901920 |
| 005 |
20181031133100.0 |
| 010 |
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|a 978-1-402-05828-8
|b HB : alk. paper
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| 010 |
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|a 1-402-05828-4
|b HB : alk. paper
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| 010 |
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|z 9781402058295
|b e-bk.
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| 010 |
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|z 1402058292
|b e-bk.
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| 100 |
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|a 20080229d2007 k y0frey0103 ba
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| 101 |
0 |
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|a eng
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| 102 |
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|a NL
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| 105 |
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|a a a 001|y
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| 106 |
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|a r
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| 200 |
1 |
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|a Digital VLSI systems design
|b Texte imprimé
|e a design manual for implementation of projects on FPGAs and ASICs using Verilog
|f Seetharaman Ramachandran
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| 210 |
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|a Dordrecht, Netherlands
|a [London]
|c Springer
|d cop. 2007
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| 215 |
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|a 1 vol. (xxii-709 p.)
|c ill.
|d 24 cm
|e 1 CD-ROM
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| 300 |
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|a CD-ROM contains all verilog codes and Matlab source codes provided in the book, command summaries for Modelsim, Synplify and Xilinx tools, and a summary of the usage of RTL Verilog codes
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| 300 |
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|a "Solution manual for the assignments ... is available to teachers from the publishers or on their website"--P. xxii
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| 301 |
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|a OHX
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| 320 |
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|a Bibliogr.. Index
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| 606 |
|
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|3 PPN027895823
|a Circuits intégrés à très grande échelle
|3 PPN027723275
|x Conception assistée par ordinateur
|2 rameau
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| 606 |
|
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|3 PPN028716248
|a Structure logique
|2 rameau
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| 606 |
|
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|3 PPN034756957
|a Réseaux logiques programmables par l'utilisateur
|2 rameau
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| 606 |
|
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|3 PPN030150175
|a Circuits intégrés à la demande
|2 rameau
|
| 606 |
|
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|3 PPN050283170
|a Verilog (langage de description de matériel informatique)
|2 rameau
|
| 676 |
|
|
|a 621.395
|v 22
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| 680 |
|
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|a TK7874.75
|b .R36 2007
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| 700 |
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1 |
|3 PPN12190315X
|a Ramachandran
|b Seetharaman
|4 070
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| 801 |
|
3 |
|a FR
|b Abes
|c 20080229
|g AFNOR
|
| 801 |
|
0 |
|b UKM
|g AACR2
|
| 801 |
|
2 |
|b OHX
|g AACR2
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| 930 |
|
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|5 441092105:329351125
|b 441092105
|j u
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| 998 |
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|a 495234
|
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