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| LEADER |
01490cam a2200433 4500 |
| 001 |
PPN117899771 |
| 005 |
20151006031200.0 |
| 010 |
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|a 978-0-12-373551-5
|b Rel.
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| 010 |
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|a 0-12-373551-3
|b Rel.
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| 020 |
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|a US
|b 2006103541
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| 020 |
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|a GB
|b A707930
|
| 035 |
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|a ocm77573915
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| 100 |
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|a 20071001d2007 u y0frey0103 ba
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| 101 |
0 |
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|a eng
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| 102 |
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|a NL
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| 105 |
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|a a a 001|y
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| 200 |
1 |
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|a ESL design and verification
|e a prescription for electronic system-level methodology
|b Texte imprimé
|f Brian Bailey, Grant Martin, Andrew Piziali
|
| 210 |
|
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|a Amsterdam
|a Boston
|c Morgan Kaufmann
|d cop. 2007
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| 215 |
|
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|a 1 vol. (XXV-462 p.)
|c ill.
|d 24 cm
|
| 225 |
2 |
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|a The Morgan Kaufmann series in systems on silicon
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| 301 |
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|a YDXCP
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| 320 |
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|a Bibliogr. Index.
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| 410 |
|
| |
|t The Morgan Kaufmann series in systems on silicon
|
| 517 |
| |
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|a Electronic system-level design
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| 606 |
|
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|3 PPN027337510
|a Microélectronique
|2 rameau
|
| 606 |
|
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|3 PPN027223221
|a Circuits intégrés
|2 rameau
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| 606 |
|
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|3 PPN027794725
|a Conception et construction
|2 rameau
|
| 676 |
|
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|a 621.3815
|v 22
|
| 680 |
|
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|a TK7895.E42
|b B326 2007
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| 700 |
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1 |
|3 PPN112226892
|a Bailey
|b Brian
|4 070
|
| 701 |
|
1 |
|3 PPN074283685
|a Martin
|b Grant
|4 070
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| 701 |
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1 |
|a Piziali
|b Andrew
|4 070
|
| 801 |
|
3 |
|a FR
|b Abes
|c 20071002
|g AFNOR
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| 801 |
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1 |
|a US
|b OCLC
|g AACR2
|
| 801 |
|
2 |
|a FR
|b AUROC
|g AFNOR
|
| 801 |
|
0 |
|b DLC
|g AACR2
|
| 801 |
|
2 |
|b BAKER
|g AACR2
|
| 930 |
|
|
|5 441092105:321565584
|b 441092105
|j u
|
| 998 |
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|a 509836
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